The present document is based on Japanese Priority Document JP 2002-285321, filed in the Japanese Patent Office on Sep. 30, 2002, the entire contents of which being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and, in particular, relates to a fabrication method of a semiconductor device, in which trench wirings and connection holes are formed by a fine pattern processing.
2. Description of Related Art
Copper has been used as a wiring material in order to meet demands for a semiconductor circuit operating at a higher speed and at a lower power consumption. Due to difficulty in etching copper, a dual damascene process in which holes and trenches for forming wirings and via-plugs are formed in an interlayer insulating film and copper is filled into the holes and the trenches at the same time has been commonly used. The dual damascene process includes a via-first approach in which a via-plug is formed first and a trench-first approach in which a wiring trench is formed first. Among them, the via-first approach is widely employed because of its easiness in dimension control and overlay control during patterning processes.
A conventional example of the via-first approach of the dual damascene process will be explained with reference to cross sectional views in FIGS. 8A to 8H showing fabrication process steps.
As shown in FIG. 8A, on a substrate 111, a first etching stopper film 121, a first interlayer insulating film 122, a second etching stopper film 123, a second interlayer insulating film 124, and a hard mask film 125 are stacked in this order.
Next, as shown in FIG. 8B, a connection hole (via hole) 126 penetrating from the hard mask film 125 to the lower most first etching stopper film 121 is formed by an optical lithography process and a dry etching process.
Subsequently, as shown in FIG. 8C, an upper surface of the hard mask film 125 is coated with a resin for etching stopper to form a resin film 127 on the surface of the hard mask film 125, and a lower portion of the connection hole 126 is filled with the resin film 127.
After having formed a resist film 128 on the resin film 127 as shown in FIG. 8D, a trench-like wiring pattern 129 is formed in the resist film 128 by the lithography process.
Next, as shown in FIG. 8E, using the resist film 128 as a mask, the resin film 127 exposed at a bottom of the trench-like wiring pattern 129, the resin film 127 formed on a side wall of the connection hole 126, the hard mask film 125 and the second interlayer insulating film 124 are dry-etched to form a wiring trench 130. This etching process stops on the etching stopper film 123. In addition, the resin film 127 filling the bottom of the connection hole 126 serves as a stopper in the etching process of the hard mask film 125 and the second interlayer insulating film 124 so that the substrate 111 immediately under the first etching stopper film 121 is prevented from being damaged due to excessive etching of the first etching stopper film 121. The first etching stopper film 121 is generally formed thin to have a thickness of 20 nm to 100 nm, for example. Therefore, the first etching stopper film 121 is insufficient for serving as an etching stopper used for etching the hard mask film 125 and the second interlayer insulating film 124, and the resin film 127 serving as the etching stopper is required.
Then, the resist film 128 and the resin film 127 are removed by an oxygen ashing as shown in FIG. 8F.
Next, as shown in FIG. 8G, the entire surface of the films is dry-etched so as to remove the second etching stopper film 123 exposed at a bottom of the wiring trench 130 and the first etching stopper film 121 exposed at a bottom of the connection hole 126. At this time, an upper portion of the hard mask film 125 on the top is etched.
Subsequently, as shown in FIG. 8H, inner walls of the connection hole 126 and the wiring trench 130 are coated with thinly formed metal barrier layer 131 and Cu plate seed layer (not shown) so as to fill the connection hole 126 with copper by plating. Thereafter, by a CMP (chemical mechanical polishing) process, excessive copper on the surface is removed. At this time, the hard mask film 125 (see FIG. 8G) serves as a polishing stopper in the CMP process. Subsequently, the hard mask film 125 (see FIG. 8G) is removed by another CMP process under different conditions from the case of copper. In accordance with the above processing, a trench wiring 132 made of copper is formed in the wiring trench 130 and a plug 133 made of copper is formed in the connection hole 126 so that the dual damascene structure is completed.
It is noted that in order to reduce wiring delay, an organic film having a low relative dielectric constant is suggested for the interlayer insulating film. However, in a case where an organic film is used for the interlayer insulating film, there may occur a problem that, because the resin film and the resist film filled in the connection hole are also organic films, the organic interlayer insulating film is stripped off together with the resin film and the resist film due to a line width error or a positioning error in the lithography process.
As a countermeasure for such a problem, a method has been suggested in which, after a hole is formed in an interlayer insulating film, an inorganic film is formed by a sputtering process or a CVD (chemical vapor deposition) process so as to form an organic interlayer insulating film, as disclosed in Japanese Patent Application Publication Hei 11-154703.
According to the method, as shown in FIG. 9A, on an insulating film 213 on which a wiring 212 is formed, an etching stopper film 221 covering the wiring 212, an interlayer insulating film 222, an intermediate hard mask film 223, an interlayer insulating film 224 and a hard mask film 225 are sequentially stacked in this order. After a hole 226 penetrating from the hard mask film 225 to the interlayer insulating film 222 on the etching stopper film 221 is formed, an inorganic oxide film 227 is formed on an upper surface of the hard mask film 225 and an inner wall of the hole 226 by a sputtering process. Next, after an organic anti-reflection film 228 is formed on the inorganic oxide film 227 by coating and a resist film 229 is formed further thereon, a trench wiring pattern 230 is formed on the resist film 229.
According to the technique disclosed in Japanese Patent Application Publication Hei 11-154703, the inorganic oxide film 227 is thickly formed by the sputtering process to be overhung at an opening of the hole 226 so as not to allow the organic anti-reflection film 228 come inside the hole 226.
Furthermore, as shown in FIG. 9B, the organic anti-reflection film 228 and the inorganic oxide film 227 are anisotropicly etched using the resist film 229 as a mask. The inorganic oxide film 227 in the hole 226 is etched to be lower than the intermediate hard mask film 223. At this time, the inorganic oxide film 227 on a bottom of the hole 226 is etched at the time of etching the inorganic oxide film 227 on an inner wall of the hole 226.
Next, the hard mask film 225 is dry-etched using the resist film 229 as a mask, as shown in FIG. 9C. At this time, there may occur a problem that the etching stopper film 221 thereunder is too much etched to damage the copper wiring 212 under the etching stopper film 221. The hard mask film 225 serves as a covering film for protecting the interlayer insulating films 222 and 224 at the time of finally etching the etching stopper film 221 and as a stopper film in the CMP process after filling the copper in the hole 226. Therefore, the hard mask film 225 should be formed thicker than the etching stopper film 221, and if the etching stopper film 221 is not covered, the etching stopper film 221 is penetrated when the hard mask film 225 is etched.
As described above, in forming a dual damascene wiring structure according to the via-first approach, there is a problem that in a case of using an organic film as an interlayer insulating film, a resist film cannot be stripped off at a lithography step for forming a trench wiring. Furthermore, even if an inorganic oxide film if formed to have a smaller opening at a hole, there is a problem that in a later step of etching the inorganic oxide film, an etching stopper film covering a copper wiring is etched so that the copper wiring is damaged.
The present invention provides a fabrication method of a semiconductor device in order to solve the above-described problems.
A fabrication method of a semiconductor device of the present invention includes: a step of forming a connection hole in an interlayer insulating film including an organic insulating film; a step of forming an inorganic film covering an upper surface of the interlayer insulating film and an inner surface of the connection hole; a step of forming an organic film filling at least a bottom of the connection hole via the inorganic film on the interlayer insulating film; a step of removing the organic film in the connection hole so as to leave the organic film on a bottom of the connection hole; a step of forming a wiring trench connecting to the connection hole in the interlayer insulating film; a step of removing the organic film inside the connection hole; a step of removing the inorganic film; and a step of forming a trench wiring and a plug continuing from the trench wiring by filling a conductive material in the wiring trench and inside the connection hole.
According to the fabrication method of a semiconductor device as described above, after forming the connection hole, the inorganic film is formed to cover the upper surface of the interlayer insulating film and the inner surface of the connection hole before filling the organic film inside the connection hole. Accordingly, in the later steps, it is possible to remove the resist mask generally used as an etching mask at the time of forming the wiring trench and the organic film filled inside the connection hole without damaging the interlayer insulating film including the organic insulating film by a conventional method. Accordingly, even in a case where an error occurs in a lithography step and a need for reproducing another resist film arises, it is possible to reproduce a resist film without damaging the interlayer insulating film. In addition, when removing the organic film, since a wiring layer formed on the bottom of the connection hole is protected by the inorganic film covering the inner surface of the connection hole, even if the organic film is removed using oxygen plasma, the wiring layer on the bottom of the connection hole is not oxidized.